One step in the manufacture of integrated circuit devices is known as “packaging” and involves mechanical and environmental protection of a semiconductor chip which is at the heart of the integrated circuit. Such packaging includes the electrical interconnections between predetermined locations on the silicon chip and external electrical terminals. One new process for packaging such chips seeks to package the chips and create solder bump electrical connections to the chip while the chips are still in place on an un-singulated wafer. By fabricating and packaging chips together in this manner the size of the final chip package is substantially reduced.
One currently used approach for chip fabrication is described hereinbelow. FIG. 1 depicts a semiconductor wafer 101 having a multiplicity of semiconductor integrated circuit dies 102 formed thereon. FIG. 2 is a simplified depiction of one example of such an integrated circuit die 102. The die 102 includes a plurality of electrical contact pads 103 (also referred to as input/output (I/O) contacts) formed thereon. The electrical contact pads 103 facilitate electrical connection of the die 102 with off-chip circuitry, such as printed circuit boards (PCB's) or other electronic devices. If such integrated circuit dies 102 and their associated electrical connections can be formed together on a wafer, numerous process advantages can be had.
Thus, many methodologies for such wafer-scale or wafer level chip scale packages are under development. One existing methodology is described herein as an example. FIG. 3(a) is a simplified illustration of a portion of semiconductor die during an example wafer-scale packaging process. As previously indicated, a wafer has a multiplicity of semiconductor integrated circuit dies formed thereon. The depicted semiconductor die 301 has an electrical contact pad 302 formed thereon. The contact pads 301 are commonly formed of aluminum. The contact pad 301 is electrically connected to electrical circuitry (not shown in this view) of the die 301 (e.g., using the via 303).
As depicted in FIGS. 3(b) & 3(c), a passivation layer 304 is formed over the substrate (including the die 301 and associated electrical contact pads 302). Such passivation layers 304 can be formed of numerous dielectric materials (e.g., SiO2, low-K dielectrics, and other passivation materials). One preferred passivation material is benzo-cyclo-butene (BCB). Conventional techniques (e.g., spin coating, etc.) can be used to form the passivation layer 304. In some implementations, the BCB passivation layer is formed about 5-6 microns thick. Using conventional photolithographic processes, openings 305 are formed in the passivation layer 304. The openings 305 are configured such that they are in register with the underlying electrical contact pads 302.
FIG. 3(d) shows the formation of an adhesion layer 306 designed to provide good adhesion with the underlying aluminum electrical contact pads 302 and also provide good adhesion to subsequently formed solder connections. This adhesion layer 306 is also referred to as under bump metallization (UBM). Commonly, the UBM 306 is formed of a multi-layer structure. In the depicted embodiment, the UBM 306 includes an aluminum first layer 307, formed on the electrical contact pads 302, a nickel/vanadium (Ni/V) alloy second layer 308 formed on the first layer 307, and a copper third layer 309 formed on the second layer 308. Commonly, the UBM 306 is formed by successive depositions of the first, second, and third layers onto the entire wafer. Subsequently, these layer are photolithographically patterned and then etched so that the UBM 306 remains only on the electrical contact pads 302. Such photolithographic patterning and subsequent etching is accomplishing using ordinary techniques known to persons having ordinary skill in the art.
With respect to FIGS. 3(e), 3(f), and 3(g) solder bumps are formed at various points throughout the entire wafer. Ordinary direct ball attach methods cannot be used when the solder bump size becomes less than about 300 micron (μm). Thus, so-called solder screen printing technologies are used to form sufficiently small bumps. Many examples of suitable processes are well known to those having ordinary skill in the art. The depicted process uses screen-printing to form a multiplicity of solder bumps throughout the entire wafer. This conventional process and some of its limitations are described below. FIG. 3(e) is a simplified depiction of a portion of a single die 301 on a wafer. In order to form solder bumps over the entire surface of the wafer, a photoresist pattern 311 is formed over the entire surface of the wafer. The photoresist pattern 311 functions as a template for the placement of the solder bumps. The photoresist pattern 311 has a pattern of openings 312 formed in registry with the underlying electrical contact pads 302. The pattern of openings is typically formed with conventional photolithographic techniques. As shown in FIG. 3(f), solder paste 313 is screen printed into the openings 312 formed in the photoresist pattern 311. As shown in FIG. 3(g), the solder paste 313 is reflowed and the photoresist pattern 311 is removed to leave a pattern of appropriately positioned solder bumps 315.
It is the screen print application of solder paste that presents certain process difficulties in known methodologies. These difficulties can be more easily understood with respect to FIGS. 4(a)-4(d). FIGS. 4(a)-4(d) are simplified schematic plan views of a semiconductor wafer during a solder bump forming process. FIG. 4(a) is a simplified schematic plan view of a semiconductor wafer 401 having a layer of photoresist material formed thereon (e.g., before the patterning step of FIG. 3(e)). FIG. 4(b) depicts patterning of the photoresist layer to form a pattern of openings 402 that expose the underlying electrical contact pads of the semiconductor dies. Also, shown in FIG. 4(b) is a dashed line which schematically demarcates the outer edge 403 of a screen print stencil used in the application of solder paste into the openings 402. Because the pattern of openings 402 formed in the photoresist is formed using photolithographic stepper device the pattern of openings 402 extends beyond the outer edge 403 of a screen print stencil. This has significant consequences that will be discussed later.
After the application of solder paste during a conventional screen printing process, the openings 402 are filled with solder paste. It is noted that during the screen printing process excess solder paste is applied to the stencil and the wafer. The excess solder paste is removed by scraping the paste from the stencil. However, this does not remove all the paste from the wafer 401. Thus, as depicted in FIG. 4(c) a ring 404 of excess solder paste is formed around the outer edge of the now removed stencil. Additionally, certain edge openings 402′ near the edge of the photolithographic pattern extend into the portions of the wafer where the ring 404 of excess solder paste is formed. During reflow, these edge openings 402′ form excessively large solder bumps relative to solder bump formed in the other openings 402. This phenomenon is schematically illustrated in FIG. 5 which shows an oversize edge solder bump 501 formed by the excess solder pooling from the ring of excess paste formed on the outer edge of the wafer. This is in comparison to the smaller bumps 502 formed over much of the rest of the wafer surface. The presence of the oversize bumps causes a myriad of problem. Examples include, but are not limited to, difficulties in correctly aligning the chip when it is to be attached to other devices or PCB's. Also, the chips suffer from breakage during further processing due to the fact that the chips cannot be laid flat for processing and the resulting strains placed on the chips during such processing cause breakage.
FIG. 4(d) illustrates one conventional approach for addressing these above problems. FIG. 4(d) illustrates the wafer of FIG. 4(c) after the edge of the wafer is scraped to remove excess solder paste. Currently, this must be done by hand. Moreover, current scraping processes result in the contamination of the pallets that hold the wafers. Additionally, automated approaches result in worse contamination. Moreover, even after scraping, a thin band 405 of solder paste still remains at the portion of the wafer defined by the outer edge 403 of a screen print stencil. This thin band 405 still contains enough excess solder paste to cause the formation of oversize solder bumps.
What is needed is a manufacturable wafer scale process capable of forming uniformly sized solder bumps of less than about 300 μm in size on the electrical contacts of a plurality of semiconductor dies. Moreover, the process should prevent the formation of oversize solder bumps caused by the pooling of excess solder paste from around the edges of the wafer. Also needed are semiconductor wafer structures enabling the fabrication of uniform solder bumps.